1. Technical Field
The disclosed embodiments relate generally to divide-by-two divider circuits.
2. Background Information
In one type of RF receiver such as might be found in a cellular telephone, a crystal oscillator outputs a high quality reference clock signal. The reference clock signal from the crystal has low frequency drift and has low clock edge jitter. A Phase-Locked Loop (PLL) circuit receives this reference clock signal and generates therefrom a higher frequency VCO output signal. The VCO output signal has a programmable frequency that is tunable in a tunable range (for example, from 1 GHz to 3 GHz). The best Voltage-Controlled Oscillators (VCOs) in terms of being low phase noise VCOs for use in such PLLs generally output sinusoidal differential signals. This type of low-noise VCO is therefore used. The mixer that performs downconversion in the receive chain of the receiver may, however, be best driven using I and Q quadrature signals, where each of the quadrature signals has a low duty cycle (for example, a 25% duty cycle). A divide-by-two divider circuit is therefore sometimes employed to receive the sinusoidal differential output signal from the VCO and to generate therefrom the low duty cycle I and Q signals for the mixer.
There are, however, many different types of divide-by-two divider circuits that might be employed. Each type of divide-by-two divider circuit has some more desirable qualities and has other less desirable qualities. The determination of what type of divide-by-two divider to use generally involves trade-offs depending on the application. Ideally, in one particular cellular telephone receiver application, the divider-by-two divider should: generate low duty cycle I and Q signals, consume only a small amount of power, output I and Q signals that have short rise and fall times, introduce only minimal noise jitter into the I and Q output signals, operate from a low supply voltage as low as 1.0 volts, and output I and Q signals that transition from rail to rail.
FIG. 1 (Prior Art) is a diagram of a divide-by-two divider 1 referred to here as a Razavi divider. For additional information on a Razavi divider, see: “Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops In Deep Submicron CMOS”, by Behzad Razavi et al., IEEE Journal of Solid-State Circuits, Vol. 30, No. 2, pages 101-109, February 1995. The Razavi divider 1 involves P-channel transistors 2-5 and N-channel transistors 6-13. The Razavi divider outputs low duty cycle (25%) I and Q signals, and is relatively fast, and outputs rail-to-rail signals, but the Razavi divider consumes an undesirably large amount of power and introduces more phase noise into the output signals I and Q than is desired. Moreover, it is generally difficult to implement such a Razavi divider that operates reliably over process and temperature from a low 1.0 volt supply voltage.
The Razavi divider 1 of FIG. 1 includes a first latch 14 on the left, and a second latch 15 on the right. The two latches 14 and 15 are interconnected as shown. The divider receives a differential signal IN and INB, and outputs four single-ended signals P1, P2, P3 and P4. The frequency of each of the single-ended output signals P1, P2, P3 and P4 is of half the frequency of the differential input signal IN and INB.
FIG. 2 (Prior Art) is a table that sets forth an operation of the Razavi divider of FIG. 1. The first row of the table indicates a starting condition in which the input signals IN and INB are 0 and 1, respectively. The IN and INB signals then transition to the opposite values as indicated in the second row. When INB transitions from the 1 of the first row to the 0 of the second row at time T2, the P-channel transistors 2 and 3 are turned on. Current flow from a VCC conductor through transistor 2 to node 16 causes the voltage of P1 on node 16 to rise and to change from a 0 to a 1. Note that the value of P3 is indicated to change from a 0 to the 1 when transitioning from the first row of the table to the second row of the table. The transitioning of P3 to a 1 causes the voltage on the gate of N-channel transistor 10 to be high, thereby turning on N-channel transistor 10. This in turn causes signal P2 to transition low. At this point, P3 is high, and the other three signals P1, P2 and P4 are low. This condition is reflected in the second row of the table of FIG. 2 and persists until the next change in the input signals IN and INB.
When the input signal IN transitions from a 1 to a 0 as indicated by the second and third rows of the table of FIG. 2 at time T3, P-channel transistors 4 and 5 are turned on. This causes P4 to transition from 0 to 1. The signal P4 is supplied onto the gate of N-channel transistor 9. N-channel transistor 9 is therefore turned on, and signal P3 is made to transition from 1 to 0. At this point, output signal P4 is high, and the other three output signals P1, P2 and P3 are low. This condition is reflected in the third row of the table and persists until the next change in the input signals IN and INB.
When input signal INB transitions from a 1 to a 0 as indicated by the third and fourth rows of the table at time T4, P-channel transistors 2 and 3 are turned on. This causes output signal P1 to transition from 0 to 1. The signal P1 is supplied onto the gate of N-channel transistor 13. N-channel transistor 13 is therefore turned on, and output signal P4 is made to transition from 1 to 0. At this point, output P1 is high, and the other three output signals P2, P3 and P4 are low. This condition is reflected in the fourth row of the table of FIG. 2 and persists until the next change in the input signals IN and INB.
When input signal IN transitions from a 1 to a 0 as indicated by the second and third rows of the table of FIG. 2 at time T5, P-channel transistors 4 and 5 are turned on. This causes P2 to transition from 0 to 1. The signal P2 is supplied onto the gate of N-channel transistor 6. N-channel transistor 6 is therefore turned on, and signal P1 is made to transition from 1 to 0. At this point, output P2 is high, and the other three output signals P1, P3 and P4 are low. This condition is reflected in the fifth row of the table of FIG. 2 and persists until the next change in the input signals IN and INB.
As the differential clock signal (IN and INB) continues to toggle, operation of the divider repeats through the states indicted in the rows of the table of FIG. 2.